To perform a write operation on a memory such as a RAM (RAM=random access memory=memory with random access), an address, which is assigned to the memory cell in which the data are to be stored, is typically entered in the storage system via an address line. Using the address a column and row line of the storage system is selected and put into an active state, so that the appropriate data can be written into the assigned memory cell.
The ongoing development of data processing devices in respect of processing speeds and the amounts of data made it necessary to design RAMs of ever increasing capacity and higher data throughput.
Activation of the appropriate column and row line always entails a certain expenditure of time, however, making it desirable to transfer as much data as possible each time the storage system is accessed in order to make the most effective use of the data line and to maximize the in-use time of the data line.
A known method of performing a write access on the storage system is to transfer data bundles of successive data blocks, which are stored e.g. in successive memory cells of the same line of the memory. This method increases the data throughput since a bundle of data blocks is transferred for each access operation while e.g. the column address line is activated only once.
Since, however, it is not always desirable or necessary to store a whole bundle of data blocks in one write operation, a data mask signal, which is assigned to a data block, is used to mask data for the write and read instructions.
In the read mode the data mask signal has a latency (delay time) of two clock signal units and is used to put the data output buffer into a HiZ-like state in accordance with an out-put enable signal.
In the write mode the data mask signal has a latency of zero clock signal units in known storage systems and acts as a word mask. The input data of a data block are written into a memory region if the data mask signal is in a logically low state, while a write operation to the memory region is blocked if the data mask signal is in a logically high state.
In addition, in x16 operation, i.e. for a data bus line with 16 bits, in known storage systems a method is used which employs two data mask signals so as to enable bytewise control to be achieved. The first data mask signal acts on the first eight bits of a data block and the second data mask signal acts on the last eight bits of the data block. This makes one-byte-level control possible for a 16 bit data line, so that e.g. just a single byte, i.e. eight bits, of the data block is written into the memory.
To enable a high data throughput to be achieved, it is desirable that the data should be transferred with a higher frequency, e.g. double the frequency of the clock signal.
However, this requires that the data mask signal be generated and transmitted with the frequency of the data blocks since, in known methods, the information of the data mask signal always refers to a single data block. Further, at high data signal transfer frequencies a transfer line which is optimized for high frequencies is needed for the data mask signals. In addition, the generation of the data mask signal with the time demands of an increased frequency adjusted to that of the data signal is complicated and costly. Another point is that existing equipment which is present in a processor system and adjusted to the simple clock signal frequency cannot be used.